EDN

Hierarchical test improves pattern application efficiency

For over 15 years, I've been a big proponent of hierarchical test. Hierarchical test is the commonly used term for creating DFT (design-for-test) features and test patterns at lower level circuit ...
Hackaday

test pattern

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...
Electronic Design

Combining Logic BIST and Scan Test Compression

Small geometries have projected IC technology into an era where test has become a crucial part in the chip design process and have introduced new challenges needing solutions that use already ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...